UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for making very structured VHDL-based testbenches.

Overview, Readability, Maintainability, Extensibility and Reuse are all vital for FPGA development efficiency and quality. UVVM VVC (VHDL Verification Component) Framework was released in 2016 to handle exactly these aspects.

UVVM consists currently of the following elements:

• Utility Library

• VVC (VHDL Verification Component) Framework - Including Utility Library

• BFMs (Bus Functional Models) to be used with any part of UVVM (See below for currently supported interfaces from Bitvis)

• VVCs to be used with UVVM VVC Framework and may be combined with BFMs (see overview below)